Philippe Darche "Microprocessor 4"

Figure 1.8.Instruction with an operand field

It is one of the fastest addressing modes since the value is included in the instruction and there is therefore no additional access to the main memory to fetch the operand accessed by another addressing. But this value is a constant. In addition, from the perspective of programming, the change of value means a modification in the program since the value field cannot be a destination. The extent of the values (in the sense of Chapter 2 (#ud6d44f92-6a6a-555e-9f28-1b50c4c9828d) of Darche (2000)) is limited by the number of bits remaining after subtraction of those bits reserved for coding the operation itself (a similar limitation for the address for direct and relative addressing). In its extended or long version, the format is double that of a short format. The possibility of choosing makes it possible to decrease the number of clock cycles to fetch the operand. An alternative to this mode is register addressing, which contains a constant value, which is materially fixed. This is the current practice with RISC microprocessors (this will be covered in a future book by the author on microprocessors) such as Arm

, whose register r0 contains the null value (cf. В§ V3-3.1), which can serve for initialization and avoids time-consuming external access to the main memory.

1.2.2. Register addressing

The use of registers makes it possible not to slow the microprocessor down since the registers are integrated. An instruction that uses them in addressing mode will only require external access to fetch the instruction code. It is possible to address a register in two ways, explicitly and implicitly.

1.2.2.1. Explicit addressing

The operand field operand(s) R specifies the registers used for execution. It is sometimes called register (direct) addressing, the term “direct” indicating that the referencing in the register is found in the instruction coding, as for the direct memory address (Figure 1.9). These registers are accessible to the programmer. There is no effective address since the memory is not addressed, hence a fast execution of the instruction using it and a small instruction format. It is for this reason that RISC microprocessors prefer to use this mode. For other architectures, the number of registers accessible to the programmer is limited (order of size: about 20).

Figure 1.9.Execution of an instruction using register addressing from one register

The example below shows an addition in an Arm

microprocessor, which uses three registers: r0, r1 and r2:

ADD r0,r1,r2; r0 в†ђ r1 + r2

Note, a distinction can be made between Data Register Direct Addressing and Address Register Direct Addressing as for MC68000 (cf. В§ V3-3.1.1).

1.2.2.2. Implicit register addressing

To simplify the programming, some instructions use one or more registers in an extended or implicit manner. In this addressing mode, also called implicit or implied addressing mode, no operand is specified after the instruction mnemonic (cf. § 2.1). Execution of the instruction involves the reference to operand that is not joined to the operating code. One synonym is implication (Brooks 1962). The instruction format is reduced by it. One example is the dex instruction from MCS6502, which decrements its index register X. The name of this appears in the mnemonic to facilitate programming. Sometimes when the accumulators are used, this mode is called “accumulator addressing”. The example below applied to MC6809. The accumulator B specified by the last letter of the mnemonic receives a value expressed in hexadecimal base.

LDB #$FA; B в†ђ FA16

If the name of the registers does not appear in the mnemonic, then only a detailed reading of the technical documentation can specify the name of these registers. In the example below (MC6809), the instruction for multiplication mul (without operands) implicitly uses both implicit accumulator registers A and B and stores the concatenated result in these same registers, and the MSB (Most Significant Byte) is found in accumulator A, which in pseudo-code gives: A:B в†ђ A Г— B.

Another example is the instruction from 8086 mul bl, which uses the implicit register A as source and destination operands in the case of multiplication in 8-bit format (ax в†ђ bl Г— al for this example).

To generalize, an instruction lacking one or more operands found in a register (an accumulator for example) or in memory uses implicit addressing. We find this mode in machines with a single address called an accumulator or in the extreme case of zero-operand computers also called stack or pushdown-store machine (cf. В§ V1-2.7.1). By broadening the definition to registers that are not accessible to the programmer, any instruction for its execution uses the PC (Program Counter), which is therefore implicit.

1.2.3. Memory addressing modes

It is possible to address the memory in a direct, relative, indirect, indexed or based manner. Combinations of these modes are possible. Other specific modes are then presented.

1.2.3.1. Direct addressing

Direct or absolute addressing is without doubt the most natural. It can access a memory address location A defined (i.e. arranged immediately) after the instruction code in the operand field (Figure 1.10). It can therefore be considered a constant. The effective address EA is given by the following formula:

[1.1]

Figure 1.10.Instruction with direct addressing

It can be used by jump instruction to branch to a set location in the program. This mode is in fact an indirect mode with auto-incrementation using the PC (Program Counter) as an indirection register (cf. В§ 1.2.3.3 for indirection).

This mode allows for variations depending on the format of the address provided, the benefit lies in reducing the instruction's memory size. Some manufacturers thus distinguish the short mode from the extended mode, known as long mode, depending on the format of the address A, provided. In the short mode (absolute short, page zero, also known direct at Motorola, a base page (IEEE 1985)) illustrated in Figure 1.11, the address is expressed in a smaller format than that of a microprocessor. The address field may also be smaller than 3 bits, one example being the 8021 microcontroller from Intel or, classically, 8 bits in 8-bit MPUs. Page zero can be seen as a bank of registers (RF for Register File, cf. В§ V3-3.1.11.1). The MIPS firm speaks of pseudo-direct addressing. Aside from a smaller format, the second benefit lies in decreasing the number of memory accesses to fetch the instruction code and the operand address. It is equivalent to a basic addressing + displacement, as in the IBM System/370 architecture, with a null base address. One example is the MC6802 microprocessor where the address is in byte format, while the format of the MPU address bus is double. This then limits the address space to the interval [00, FF]

, hence the term “absolute short addressing” or “page zero”

(if the size of the memory page is 256 bytes). In the example below, the A register receives the content of memory location 00.

Figure 1.11.Instruction with an address at page 0

The concept of page zero addressing has been improved with direct page addressing. The direct page is now movable in a larger memory page. The start of the page is addressed by a specialized register (cf. В§ V3-3.1.1). We cite MC6809 (a page of 256 bytes in a space of 64 KiB, addressing capacity of the MPU itself, direct page (DP) register), the 65CE02 from Commodore Semiconductor Group or CSG (the same as before except that its addressing capacity is higher, base page register B) and the 65816 from the firm Western Digital Corporation (WDC) with an address over 16 bits in the direct page register D.

A direct addressing is limited in its extent for a given instruction format; there are bits reserved for coding the instruction, which should be subtracted from the bits reserved for the addressing. This limitation can be lifted if the instruction format is not limited (i.e. variable format). With extended addressing, the address belongs to the microprocessor's address space without restriction. The format is that of the address bus. It should be noted that the absolute address can be implemented with a basic address + displacement with a basic register with zero content base.

1.2.3.2. Relative addressing

Relative addressing, implied in PC (Program Counter-relative addressing), makes it possible to access a memory location relating to the current position of the program counter that, we recall, contains the address of the next instruction to be executed (Figure 1.12) after the decoding stage. This mode is in fact an indexed mode using the PC (cf. В§ 1.2.3.4 on indexing). With the following formula, we see that the effective address of the data or instruction relates to the PC by a value of d:

[1.2]

This is the favored mode for jump instructions, whether conditional or not (PC-relative branch). The relative displacement d is expressed in a signed integer representation, which is always the complement to 2

(two's complement, cf. В§ II.2.5 from Darche (2000)). Depending on the size of the displacement, the extent of the jump will be limited to (-2

, 2

-1), with n being the format of the address field. Depending on the value of n of the relative address, we will call it a short or long jump. When the processor uses segmentation (this will be covered in a future book by the author on memories), jumps can be made within a single segment (intrasegment jump) or between two segments (extra-segment jump).

Figure 1.12.Execution of an instruction in relative addressing

The example below (x86) is a negative jump. The hexadecimal value F9 represents -7 in base 10. This means that the processor will connect 5 bytes higher than the instruction address, the difference of two bytes arising from the fact that the PC has changed while the instruction was executed (incrementation of the size of this instruction, here, two bytes):

73 F9 jnc loop; PC в†ђ PC + F916

Two particular cases should be cited: jmp 00, which jumps to the following instruction since the program counter has been incremented during the decoding phase of the execution cycle (cf. § V1-3.2 and V1-3.3.2) to direct the following instruction and jump –n, where n is the instruction format (in words) underway, which implements an infinite loop. This mode is linked to PC (PC with displacement or Program Counter with Displacement for MC68000). It can be seen as an indexed mode, the indexation register being the PC (cf. § 1.2.3.4).

This mode is useful for generating the independent code of implantation in memory (position-independent code). We also speak of a translatable code (relocatable code), a topic discussed in В§ 3.1.4. It is also at the root of implantation of classic control structures of high-level languages (if__then_else, iterative structures (i.e. loops) such as while__do, repeat_until_, for__do, etc.) in assembly language.

This mode can even be used to address an operand (Figure 1.13). We cite x86 64-bit architectures with addressing called RIP (Instruction Pointer Register)- relative, ARMv8 with literal mode and MPU MC6809 with the program counterrelative mode.

Figure 1.13.Seeking an operand in relative addressing

This mode can be seen as an indirect mode auto-incrementation using the PC (Program Counter) as an indirection register (cf. В§ 1.2.3.3).

1.2.3.3. Indirect addressing

It is useful to dissociate addressing of the operand from that of the instruction code. The address may thus vary without changing the reference indicated in the instruction. This mode is used to implement the mechanism of the High-Level (programming) Language (HLL) pointer. In assembly language, the square brackets “[“ and “]” are generally used to employ this mode. Some constructors use parentheses or the character @. A memory location or register contains the address of the operand. In indirect mode or register deferred mode (register indirect or register deferred addressing

) illustrated in Figure 1.14, the effective address EA is given by the following formula:

[1.3]

Figure 1.14.Instruction with indirect register addressing

In memory indirect addressing illustrated in Figure 1.15, the final effective address EA is given by formula [1.5] (#ulink_a0780371-03bd-5465-924e-57e0bb4d2c5c). Here, it is a double indirection:

[1.4]

[1.5] (#ulink_0faf5726-8b94-5a59-8a6d-697c2475ce4a)

Figure 1.15.Instruction with indirect memory addressing

This mode of addressing generally has a greater extent than direct addressing since the addressing format m is the same as that of the data format n. It was therefore useful for the first computers, which had a restricted addressing capacity (in the case of mini-PDP-8 computers from the DEC firm of the NOVA series from Data General, for example). Another advantage is the decrease in the instruction format, thus increasing the instruction throughput. For MC6809, the constructor speaks of “extended indirect addressing”. The compiler will doubtlessly use this mode to implement the high-level language pointer mode such as C or Pascal by putting the value of the pointer (i.e. an address) in the indirection register.

An auto-increment or auto-decrement can be suggested, which can be done before (prefix “pre”) or after (prefix “post”) the instruction using it is executed. It makes it possible to implement operators directly, such as ++ and -- in the language C. This means that after execution of this operator, the value of the pointer that contains the address of the object pointed to is incremented or decremented by a value equal to the size of the pointed element. But in the MPU, the increment or decrement value is fixed at programming in low-level language. More generally, auto-increment or auto-decrement makes it possible to manage a memory index, which is useful, for example, in displacement in a data structure such as an array. Register indirect addressing with post- or pre-increment/decrement is adapted for digital signal processing to address samples.