Philippe Darche "Microprocessor 4"

This mode is in fact the one that makes it possible to implement absolute addressing mode using the PC (Program Counter) as an indirection register. It is for this reason that DEC (1983) with PDP series, which used the PC as a General-Purpose Register (GPR, cf. § V3-3.1), called it “PC absolute mode”, equivalent to an immediate indirect addressing (immediate

deferred mode or auto-increment deferred mode). The term “immediate” means that the value immediately following the instruction code addressed by the PC will be used to fetch the address of the operand (EA = PC + 2 bytes in the case of the PDP-11 mini-computer) with, afterwards, an update to the PC. This same manufacturer proposed a relative deferred mode PC addressing, that is, indirect relative addressing, which uses the PC added to a displacement to fetch the operand's address (EA = (PC

+ displacement) in the case of PDP-11).

1.2.3.4. Indexed and based addressing modes

Indexed addressing is characterized by using an Index Register (IR) that contains a reference address, called a base or offset address, making it possible to access a memory location. The content of this register, here R, is added to a displacement A specified with the instruction (Figure 1.16). The effective address EA is equal to:

[1.6]

Indexed addressing with null displacement is identical to register indirect addressing. This mode is equivalent to relative addressing if the index register is replaced by the PC (Program Counter). The index register may be implicit or designed explicitly as an operand. It can be dedicated specifically to this usage or it can be a GPR. In the former case, it is generally named X or Y (in the case of MCS6502). From the perspective of execution complexity, it adds an operation (addition) compared to the indirection. The @ symbol is generally used in assembly language to indicate this mode.

Figure 1.16.Execution of an instruction in indexed addressing with displacement (indexation “true”)

Cushman (1975) speaks of “true” and “false” indexing. Indexing is called “true” when the index address is the operand, the case in Figure 1.16 and MPUs MCS6502 and 2650 (Signetics). In the second case, the index address is in the dedicated register and the operand is the index, one example being the MC6802/MC6809 (Figure 1.17). The second field of the instruction word, called a “modifier” in Simpson and Terrell (1987) has an 8-bit format, while the index register format has 16 bits. Some manufacturers such as Motorola consider the relative address as an indexed mode, the indirection register being the PC (Program Counter, cf. § 1.2.3.3).

Figure 1.17.Execution of an instruction in indexed addressing with displacement (false indexing)

As for indirection with auto-increment or auto-decrement, auto-indexing can be suggested with the addition of an integer A to the value of the register R. The designer of M68HC12 speaks of pre-decrement and post-decrement indexed. At each execution, we will have:

[1.7]

Relative addressing is similar to an indexed addressing by the PC (Program Counter). It is for this reason that DEC (1983) called it “PC-relative addressing mode”.

Scaled indexed addressing mode makes it possible to multiply the content of the index register by a constant 1, 2, 4 or 8, for example, for 80386. This facilitates management of data structures in high-level languages as an array, a structure or record.

Base (plus) offset addressing arises from the principle above except that the index register is replaced by a base register (Figure 1.18), hence its other name: base register addressing. Intel uses the BX and BP (Base Pointer) for x86, the first addresses the data segment and the second addresses the stack. The IBM z System mainframe computer uses 16 General-Purpose Registers (GPR) in 64-bit format as a base register and the displacement is specific to the 12-bit format. At its origin, this mode made it possible to extend the address space. Today, this is no longer necessary.

Figure 1.18.Execution of an instruction in base addressing with displacement

The difference between these two modes is more semantic than applicable to calculating the effective address. The index varies starting from a given index address with the instruction, while the base address is constant (hence its name) and an offset is provided with the instruction. Moreover, Intel uses the terms “base” and “indexed” for base addressing. Moreover, if no offset is specified with the instruction, Intel (1989) names the 8086 base and indexed addressing without offset “indirect register addressing”. Often, in RISC microprocessors such as Arm

, the r0 register contains the constant 0, thus avoiding an immediate addressing using a main memory access that takes a great deal of time. If it is used as a base register, the addressing becomes absolute. The base mode is similar to segmented addressing (this will be covered in a future book by the author on memories). Another means of differentiating these two addressings is that there is no auto-increment with base addressing.

Calculation of the effective addressing depends on the storage order or endianness (cf. В§ V1-2.2.1) of the address' bytes. Thus, MCS6502 with a little- endian order is favored because the addition is carried out starting from the LSBs.

1.2.3.5. Combinations of addressing modes

It is possible to combine the addressing modes above. Some processors offer indirect addressing with indexing. The associated terms “pre-indexing” and “post-indexing” will qualify at what step of the address calculation the indexing will apply. Pre-indexing means that indexing is carried out on the indirection address (pre-indexed indirect addressing mode), hence the second name, “indexed indirect addressing mode”.

We will have:

[1.8] (#ulink_76206201-1c59-540f-ac0c-bb00333b9311)

Figure 1.19 shows the mechanism. One example was MCS6502, which included two registers called “index registers X and Y” even though X has already served for indirection. Its designer calls this mode (indirect,X), which is justified by the relationship [1.8] (#ulink_60ed9db4-8412-5d42-9b5a-43387193b82e). It was also suggested by MC6809. DEC used the term “index deferred addressing mode”.

Figure 1.19.Indirect indexed addressing or pre-indexing

Post-indexed indirect addressing mode or indirect indexed addressing mode applies indexing after indirection, as illustrated in Figure 1.20. We will have:

[1.9]

[1.10] (#ulink_f00a77c4-12b6-553a-ae02-5c87405f1907)

Figure 1.20.Indirect indexed addressing or post-indexing

The peculiarity of MCS6502 is that it used zero-page addressing as the address field was limited to 8 bits and the indexing occurred only on the lower part of the address (Figure 1.21). Its designer calls this mode (indirect),Y, which is justified by the relationship [1.10] (#ulink_c2111fcc-fd4b-5e8c-a2be-149d5b281a2c).

Figure 1.21.Indirect indexed zero-page addressing of MCS6502

A representative, penultimate example is MC6809, which offers 18 variations in mode, combining indexed and indirect addressings with the possibility of automatic post-increment or pre-decrement. This post-increment or pre-decrement is useful for managing a stack's pointer. Table 1.2 summarizes the possible combinations. R represents one of the four registers that can be used for indexing, the classics X and Y and the stack pointers user U and material S. Note the addressings using the program counter at the end. The offset is expressed in complement to 2

representation.

Indexed and based addressings with or without offset (based indexed plus displacement addressing mode) can be combined, thus offering, for example, 17 possible variations in the case of microprocessor x86. One example of this use is addressing an array of records, of a vector or of a structure, the base pointing the start of the array and index, an element of the array and the displacement, a field of the element.

Table 1.2.Combined MC6809 addressing modes

1.2.4. Other addressing modes

Other modes have been introduced to provide a high-level functionality or to adapt to a specific domain such as digital signal processing (cf. В§ V3-5.2), to a specific mechanism of a processor or to a component such as an I/O controller (cf. Chapter 3 (#u7c2b72c8-9f58-5cf8-89c8-95a6d038d61e) of Darche (2003)) or a microcontroller (cf. В§ V3-5.3). Moreover, other modes belong to high-level languages. To finish, some obsolete modes are presented.

1.2.4.1. Memory-to-memory addressing

The memory-to-memory transfer functionality is possible in a von Neumann- inspired MPU, but it should be seen as exceptional. This is the continuity of the tendency of CISC processors to implement high-level functionalities in the material. Intel calls this mode “string addressing” for its 8086. It involves addressing the characters of a string, that is, of an array of characters by indirection using both its pointer registers SI (Source Index) and DI (Destination Index). It makes it possible, among other things, to read or write a character and, whether the repeat prefix is conditional or not, to make a copy of it in the main memory. The search function in a string is also available.

1.2.4.2. (Implicit) stack addressing

Operands are found implicitly (i.e. they are not named) on the stack which is, we recall (cf. В§ 4.1), access to LIFO (Last-In/First-Out, push-in/pop-out or push- down/pop-up memory) and implemented in primary memory in modern MPU. The two primitives (i.e. functions) to access it are stacking() and unstacking(), translated into instructions respectively by push() and pop(), for example, in x86 architecture. These instructions implement, internally, an indirect addressing mechanism with the Stack Pointer register (SP), which memorizes the address at the top of the stack. The stack is implemented in main memory, but it can be implemented in the processor. The stacked element is specified with the operand. There are also specific instructions to a register, such as pha/pla (push/pull accumulator onto/from stack) from MC6800, which makes it possible to stack/destack this MPU's accumulator. MCS6502 uses php/plp (push/pull processor status on/from stack) this time for the MPU's context. By extension, stack computers do not explicitly name the operands (zero-operand, one-operand or two-operand addressing). For reading on this subject, see Koopman (1989).

The NS3200 (Hunter 1987) from National Semiconductor (NS) has broadened access to the stack by offering a mode called top-of-stack, literally “stack top”, which makes it possible to access the data of the so-called summit, since modification of the pointer is not systematic (i.e. dependent on the operation). To finish with this topic, MPUs such as the families Arm

, PowerPC or MC68000 make it possible to use General-Purpose Registers (GPR) as stack pointers. The addressing mode is of indirect type with auto-increment/decrement.

1.2.4.3. Bit addressing

The first GPPs (for General-Purpose Processor, cf. § V3-1.1) did not have specialized instructions to manipulate (set at one/zero or extraction) or to test individually the bits of an operand by conditional branching (cf. § 2.4.1). It is generally microcontrollers that possess them as they have to read or modify binary information in memory or at the input–output ports (cf. § 3.1 from Darche (2003)). Thus, the microcontroller 68HC12 from the MC6800 family from Motorola has the instructions bclr (bit clear) and bset (bit set) that initialize respectively at 0 or at 1 one position bit specified with the help of a binary mask (see exercise E2.4) in an address word A. These instructions use this mode associated with pre-studied conventional addressing modes. It should be noted that the addressing space is limited compared to other modes. The example in Figure 1.22 shows a reset at 0 for the MSb (Most Significant bit) of an I/O port in byte format implanted at the address 0F

.

Figure 1.22.Execution of an instruction in bit addressing

1.2.4.4. MMR addressing

One possibility is to manipulate I/O registers as conventional addresses (MMR for Memory-Mapped Register, literally, registers projected into memory, cf. В§ V3-3.1.1 and V3-2.1.1.1) in reduced format (page zero addressing) with fast specialized access instructions. One example is the Digital Signal Processor (DSP), reference C5000 from Texas Instruments (TI).

1.2.4.5. Addressing modes specific to the digital signal processor

Other than indirect register addressing with post- or pre-increment/decrement, two other modes are particularly adapted to digital signal processing, which justifies their implementation in DSPs. This is circular addressing and (address) bit-reversed addressing.